174 lines
5.5 KiB
C
174 lines
5.5 KiB
C
/*
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* Implement fast Fletcher4 with AVX2 instructions. (x86_64)
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*
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* Use the 256-bit AVX2 SIMD instructions and registers to compute
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* Fletcher4 in four incremental 64-bit parallel accumulator streams,
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* and then combine the streams to form the final four checksum words.
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*
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* Copyright (C) 2015 Intel Corporation.
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*
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* Authors:
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* James Guilford <james.guilford@intel.com>
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* Jinshan Xiong <jinshan.xiong@intel.com>
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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#include <linux/simd_x86.h>
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#include <sys/spa_checksum.h>
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#include <sys/strings.h>
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#include <zfs_fletcher.h>
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static void
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fletcher_4_avx2_init(fletcher_4_ctx_t *ctx)
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{
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bzero(ctx->avx, 4 * sizeof (zfs_fletcher_avx_t));
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}
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static void
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fletcher_4_avx2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
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{
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uint64_t A, B, C, D;
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A = ctx->avx[0].v[0] + ctx->avx[0].v[1] +
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ctx->avx[0].v[2] + ctx->avx[0].v[3];
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B = 0 - ctx->avx[0].v[1] - 2 * ctx->avx[0].v[2] - 3 * ctx->avx[0].v[3] +
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4 * ctx->avx[1].v[0] + 4 * ctx->avx[1].v[1] + 4 * ctx->avx[1].v[2] +
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4 * ctx->avx[1].v[3];
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C = ctx->avx[0].v[2] + 3 * ctx->avx[0].v[3] - 6 * ctx->avx[1].v[0] -
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10 * ctx->avx[1].v[1] - 14 * ctx->avx[1].v[2] -
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18 * ctx->avx[1].v[3] + 16 * ctx->avx[2].v[0] +
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16 * ctx->avx[2].v[1] + 16 * ctx->avx[2].v[2] +
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16 * ctx->avx[2].v[3];
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D = 0 - ctx->avx[0].v[3] + 4 * ctx->avx[1].v[0] +
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10 * ctx->avx[1].v[1] + 20 * ctx->avx[1].v[2] +
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34 * ctx->avx[1].v[3] - 48 * ctx->avx[2].v[0] -
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64 * ctx->avx[2].v[1] - 80 * ctx->avx[2].v[2] -
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96 * ctx->avx[2].v[3] + 64 * ctx->avx[3].v[0] +
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64 * ctx->avx[3].v[1] + 64 * ctx->avx[3].v[2] +
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64 * ctx->avx[3].v[3];
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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#define FLETCHER_4_AVX2_RESTORE_CTX(ctx) \
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{ \
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asm volatile("vmovdqu %0, %%ymm0" :: "m" ((ctx)->avx[0])); \
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asm volatile("vmovdqu %0, %%ymm1" :: "m" ((ctx)->avx[1])); \
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asm volatile("vmovdqu %0, %%ymm2" :: "m" ((ctx)->avx[2])); \
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asm volatile("vmovdqu %0, %%ymm3" :: "m" ((ctx)->avx[3])); \
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}
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#define FLETCHER_4_AVX2_SAVE_CTX(ctx) \
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{ \
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asm volatile("vmovdqu %%ymm0, %0" : "=m" ((ctx)->avx[0])); \
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asm volatile("vmovdqu %%ymm1, %0" : "=m" ((ctx)->avx[1])); \
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asm volatile("vmovdqu %%ymm2, %0" : "=m" ((ctx)->avx[2])); \
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asm volatile("vmovdqu %%ymm3, %0" : "=m" ((ctx)->avx[3])); \
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}
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static void
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fletcher_4_avx2_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
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{
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_AVX2_RESTORE_CTX(ctx);
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for (; ip < ipend; ip += 2) {
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asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
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asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
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asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
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asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
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asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
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}
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FLETCHER_4_AVX2_SAVE_CTX(ctx);
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asm volatile("vzeroupper");
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kfpu_end();
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}
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static void
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fletcher_4_avx2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
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{
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static const zfs_fletcher_avx_t mask = {
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.v = { 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B,
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0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B }
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};
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_AVX2_RESTORE_CTX(ctx);
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asm volatile("vmovdqu %0, %%ymm5" :: "m" (mask));
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for (; ip < ipend; ip += 2) {
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asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
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asm volatile("vpshufb %ymm5, %ymm4, %ymm4");
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asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
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asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
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asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
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asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
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}
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FLETCHER_4_AVX2_SAVE_CTX(ctx);
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asm volatile("vzeroupper");
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kfpu_end();
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}
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static boolean_t fletcher_4_avx2_valid(void)
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{
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return (kfpu_allowed() && zfs_avx_available() && zfs_avx2_available());
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}
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const fletcher_4_ops_t fletcher_4_avx2_ops = {
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.init_native = fletcher_4_avx2_init,
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.fini_native = fletcher_4_avx2_fini,
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.compute_native = fletcher_4_avx2_native,
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.init_byteswap = fletcher_4_avx2_init,
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.fini_byteswap = fletcher_4_avx2_fini,
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.compute_byteswap = fletcher_4_avx2_byteswap,
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.valid = fletcher_4_avx2_valid,
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.name = "avx2"
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};
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#endif /* defined(HAVE_AVX) && defined(HAVE_AVX2) */
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