123 lines
3.3 KiB
C
123 lines
3.3 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMADAPTIVITY_H__
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#define __PHYDMADAPTIVITY_H__
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#define ADAPTIVITY_VERSION "9.6.01" /*@20180814 changed by Kevin,
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*add phydm_edcca_abort func.
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*/
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#define PWDB_UPPER_BOUND 7
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#define DFIR_LOSS 7
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#define ADC_BACKOFF 12
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#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
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ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
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#define ADAPT_DC_BACKOFF 2
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#define ADAPT_DC_BACKOFF 4
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#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
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#define ADAPT_DC_BACKOFF 0
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#endif
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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enum phydm_regulation_type {
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REGULATION_FCC = 0,
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REGULATION_MKK = 1,
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REGULATION_ETSI = 2,
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REGULATION_WW = 3,
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MAX_REGULATION_NUM = 4
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};
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#endif
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enum phydm_adapinfo {
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PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
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PHYDM_ADAPINFO_TH_L2H_INI,
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PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
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PHYDM_ADAPINFO_AP_NUM_TH,
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PHYDM_ADAPINFO_DOMAIN_CODE_2G,
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PHYDM_ADAPINFO_DOMAIN_CODE_5G
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};
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enum phydm_mac_edcca_type {
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PHYDM_IGNORE_EDCCA = 0,
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PHYDM_DONT_IGNORE_EDCCA = 1
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};
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enum phydm_adaptivity_mode {
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PHYDM_ADAPT_MSG = 0,
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PHYDM_ADAPT_DEBUG = 1,
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PHYDM_ADAPT_RESUME = 2,
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PHYDM_EDCCA_TH_PAUSE = 3,
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PHYDM_EDCCA_TH_RESUME = 4
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};
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struct phydm_adaptivity_struct {
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s8 th_l2h_ini_backup;
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s8 th_edcca_hl_diff_backup;
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s8 igi_base;
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s8 h2l_lb;
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s8 l2h_lb;
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u8 ap_num_th;
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u8 adajust_igi_level;
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u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/
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u8 debug_mode;
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u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
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u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/
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boolean igi_lmt_en;
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u8 adapt_igi_up;
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u32 rvrt_val[2];
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s8 th_l2h;
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s8 th_h2l;
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u8 regulation_2g;
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u8 regulation_5g;
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boolean is_adapt_en;
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boolean edcca_en;
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s8 th_l2h_ini_mode2;
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s8 th_edcca_hl_diff_mode2;
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};
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#ifdef PHYDM_SUPPORT_ADAPTIVITY
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void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
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#endif
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void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI);
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void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
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u32 value);
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void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
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u32 value);
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void phydm_adaptivity_init(void *dm_void);
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void phydm_adaptivity(void *dm_void);
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#endif
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